1. Field of the Invention
This invention relates to microprocessor interrupts and, more particularly, to microprocessor interrupts that suspend segmentation addressing.
2. Description of the Relevent Art
The System Management Interrupt (SMI), was introduced as a mechanism to suspend execution and save the state of the processor to memory so it can be powered down. When the processor is powered on again, the state of the processor is restored and the processor transparently and instantly resumes execution. The SMI interrupt also causes the processor to switch to a different operating mode known as the System Management Mode (SMM). This allows special software, called the SMI handler, to be run. The SMI handler can preserve state information not handled automatically by the SMI (for example, floating point registers), or transfer the preserved state information to non-volatile memory, which allows the entire system to be powered down.
The SMM allows reasonably sophisticated software to be run. Therefore, an SMI can be used for a variety of functions where it is desirable to cause the processor to switch execution to another program that handles an external system event that is beyond the scope of the operating system. For example, an SMI can be used for power management of peripheral devices. When the software tries to access a peripheral that is not powered on, the system control logic generates an SMI to inhibit the instruction. The processor enters the SMM and executes code to cause the peripheral to be powered on. The SMI then restores the interrupted program which will complete the access. Another example is the emulation of peripherals. An SMI can be used to model peripherals in software or translate the protocol to model older interfaces with new peripherals.
In current .times.86 microprocessor systems, interrupts are fairly expensive due to overhead imposed by protection mechanisms and segmentation. The SMI interrupt is particularly expensive because it saves a large amount of processor state information. The latency of transferring the processor state information to memory and back again to resume the interrupted program typically costs tens of cycles. This large latency makes the SMI interrupt unfeasible for many time sensitive tasks. An improved interrupt mechanism would make a variety of new functions feasible that are currently unfeasible due to the overhead of saving and restoring the processor state of an SMI.
To reduce the overhead of an SMI interrupt, improved interrupt mechanisms allow the SMI handler to decide what state information needs to preserved. The SMI handler, however, does not have access to all state information. For example, the SMI handler does not have direct access to the segmentation descriptors, and therefore can not preserve them. Thus, the SMI interrupt mechanism must automatically preserve this information. What is desired is an interrupt mechanism that eliminates the need to preserve unnecessary state information such as segmentation information (the segment registers and their associated descriptors).